Enhancing Performance of In-order Cores with Energy Efficiency
Research Project under the guidance of Prof. Virendra Singh, IIT Bombay
Existing slice-out-of-order cores use equally-sized & static issue queues that cause dispatch stalls, leading to a reduction in energy efficiency. The distribution of program instructions among issue queues and their occupancy for SPEC CPU benchmarks was analyzed. It was observed that 50% of the equally-sized static issue queues were intermittently underutilized. The solution proposed included the use of dynamic multi-purpose queues, and optimal allocation of queue sizes based on their average and maximum occupancy. This led to 11% improvement in energy efficiency (MIPS/W) with the benchmarks.
Computer Vision and Deep Learning in Autonomous Vehicles
Research Intern with Dr Anshuman Tripathi, Senior Programme Director, Future Mobility Solutions (AVs & Electromobility), ERI@N, NTU Singapore
This research internship was related to computer vision, deep learning, and HMI for the Autonomous Vehicle prototype in the lab. The deep learning model for object detection was selected based on the analysis of accuracy, inference speed, model size, and energy efficiency of R-CNN, YOLO (v1 to v4), and SSD. YOLOv4 implementation resulted in an accuracy of 65.2% AP50 at an inference speed of 62 FPS on the MS COCO test set. The prototype is being tested in Singapore. Patent maps were developed for technology insights. The work is reported in the journal paper and accepted for publication.
Reconstruction of 3D Model of Room from Photograph
Research Intern with Prof. Lee Yong Tsui, NTU Singapore
The research internship objective was to reconstruct the 3D model of a room from its 2D photograph. The existing approach is to accurately locate the wall edges, which is challenging due to their long length. There can be a false detection of window & door edges. The novel approach was to accurately locate the corners of the room, which are only single points. It involved identifying threefold edge intersections and respective angles. The algorithm was implemented using Python & OpenCV. It prevents false detection and is robust against noise like shadows, reflections, and surface textures.
Streamlane: A Multi-channel, Flushless Cache Covert-Channel Attack by Enabling Asynchronous Collusion
Research Course Project under the guidance of Prof. Biswabandan Panda, IIT Bombay
Existing flushless cache covert-channel attacks use a single channel and do not consider noise. An approach to transmit information using multiple parallel channels is proposed, which leverages multiple cores. The optimum access pattern to fool the prefetcher is identified. An increase in bit rate by 66% was obtained on an Intel i5-8th Gen processor using multiple channels. To ensure robustness against noise, an adaptive noise controller is implemented. It dynamically changes the synchronization period in the presence of noise. This reduces the bit error rate by up to 14%.